Power management techniques are used for optimizing power consumption by exploiting hardware power saving features, e.g., clock and power gating or dynamic voltage and frequency scaling offered by most modern chips. However, activating a low power mode impacts system performances and may prevent achieving the desired quality of service (QoS). Several approaches have been provided in the art for balancing energy consumption and performances. However, most of these approaches do not reach the true optimum.
Furthermore, the prior art approaches may lead to a wrong view of the actual resource usage and availability if the resources are used in a competitive way by a plurality of entities. Consequently, this often leads to an incorrect configuration of the system. Moreover, if a hardware limit internal to the computer system is reached due to a high number of resource requests sent by different system entities, the system may behave in an incorrect way providing bad user experience.
Additionally, prior art approaches may be unable to ensure that a required QoS level can be effectively provided. The systems work in a best effort way: a device defines a QoS expectation and hopes that other entities will fulfill it. In the case where one or more entities of the system fail in providing the requested QoS level, other entities which are not aware of this failure will nevertheless try to provide the requested QoS level, and, therefore, possibly consume more power, although the requested QoS level can not be reached anyhow because of the failure of the one or more entities to provide the requested QoS level. This situation may lead to a lack of optimization of the trade-off between performances and power consumption in the system.